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FPGA as a Service:Overview of the FaaS f3 SDAccel development environment

Last Updated:Nov 20, 2023

The FPGA as a Service (FaaS) f3 SDAccel development environment is based on Xilinx SDAccel dynamic 5.0. You can develop applications in the FaaS f3 SDAccel development environment based on Open Computing Language (OpenCL). This topic describes the SDAccel development environment for f3 instances.

FaaS f3 SDAccel framework

The following figure shows the FaaS f3 SDAccel framework.

Image 29

The following table describes the components of the FaaS f3 SDAccel framework.



Xilinx OpenCL Runtime

The runtime that exposes the OpenCL API to users.


The Hardware Abstraction Layer (HAL) that adapts the OpenCL runtime to the kernel driver and manages global memory addresses.


The xocl kernel driver of Xilinx.

Host Mgnt Drv

The management driver that runs on the host to load the Field Programmable Gate Array (FPGA) kernel.

User PF

The user physical function (PF) interface that is deployed to a VM to provide users with FPGA access channels.

Mgnt PF

The management PF interface that serves as the channel for the host to access FPGAs.


The OpenCL kernel module.

FaaS f3 SDAccel development modules

Development module


Standard OpenCL framework

For more information, see OpenCL specs.

Host code development

Xilinx UG1023

Kernel code development

Xilinx UG1207


Use OpenCL on an f3 instance