The FPGA as a Service (FaaS) f3 SDAccel development environment is based on Xilinx SDAccel dynamic 5.0. You can develop and apply the FaaS f3 SDAccel development environment based on Open Computing Language (OpenCL). This topic describes the SDAccel development environment for f3 instances.
Description of the FaaS f3 SDAccel framework
- Xilinx OpenCL Runtime: the Xilinx OpenCL runtime that can be used to show OpenCL API operations
- HAL: the Hardware Abstraction Layer (HAL) where the OpenCL runtime and kernel drivers are adapted and the global memory address is managed
- XOCL Drv: the Xilinx xocl kernel driver
- Host Mgnt Drv: the management driver that runs on the host to load the Programmable Gate Array (FPGA) kernel
- User PF: the user plane physics function (PF) interface into the virtual machine to provide users with FPGA access channels
- Mgmt. PF: the management plane PF interface that serves as the channel for the host to access FPGAs
- kernel: the OpenCL kernel module
Description of the FaaS f3 SDAccel development modules
|Standard OpenCL framework||For more information, see Standard OpenCL framework.|
|Host code development||Xilinx UG1023|
|Kernel code development||Xilinx UG1207|
User guide for FaaS f3 SDAccel
For more information about the official user guide of FaaS f3 SDAccel, see Use OpenCL on an f3 instance.