This topic describes the project modes and directories used by the Register Transfer Level (RTL) compiler. This topic also provides a sample framework to help you understand how to use RTL.

Project modes

Vivado Design Suite is an integrated design environment released by a field-programmable gate array (FPGA) vendor. Vivado provides two use modes: Project Mode and NoProject Mode. The RTL compiler on F3 instances uses the NoProject mode. The following section describes the two use modes:

  • Project Mode

    In Project Mode, a .bit file is created from a project. In this mode, you must import the RTL code and constraint files to the project before you can generate the .bit file.

  • NoProject Mode

    In NoProject Mode, a .bit file is created from a .dcp file. In this mode, you must combine all the .dcp files into one .dcp file and configure the connections before you can generate the .bit file.

Main directory of a project

The directories of a project include a main directory and a source directory. The project files of the Partial Reconfiguration (PR) section are stored in the source directory, whereas the script files that run the project are stored in the main directory. The following table describes the scripts that are stored in the main directory.
Script Description
compiling.sh This script runs the entire project and generates the xclbin load file.
create_design.tcl This script can be executed in the Tcl Console of Vivado Design Suite. You must use this script to create the usr_top.v top project. Then, you must execute the run_synth.tcl script to call the create_design.tcl script and generate the custom_logic.dcp file. You must add the custom_logic.dcp files to the create_design.tcl script.
mem_design.tcl This script is executed in the Tcl Console of Vivado Design Suite to re-instantiate the intellectual property (IP) core files of double data rate (DDR) memory. This script must be used together with the config.v file. Three DDR controllers are configured in the dynamic loading area. Configure mem_design.tcl based on the actual hardware you are using to instantiate the actual DDR memory.
run_synth.tcl This script must be used together with the create_design.tcl script.
run.tcl This script is called by the compiling.sh script to run the entire project.
generate_dcp.tcl This script combines multiple .dcp files into one .dcp file to generate the final .dcp and .bit files. You can modify the policy to generate the final .dcp and .bit files.

Sample framework

Alibaba Cloud provides sample code based on the following framework. For more information about the code, see Xilinx/dma_ip_drivers. Image 27
  • You can add { PCI_DEVICE(0x1ded, 0x1004), }, to the following position in the sample code to change the ID of the device. Then, you can use the tool in the device to test your project. For more information about the AR65444 software and its tools, visit the Xilinx official website. Image 30
  • You can execute the create_design.tcl script in the Tcl Console of Vivado Design Suite to create a project and test the overall process.
  • After the entire project is created, you can use Vivado Design Suite to open the .dcp file and view project information such as information about resources, timing, and wiring.

Instructions on the RTL design on an FPGA-accelerated F3 instance

For information about the instructions on the RTL design on an FPGA-accelerated F3 instance, see Use the RTL design on an f3 instance.